The present invention relates to a technique for fabricating a semiconductor integrated circuit device, particularly to a technique that can be effectively applied to a semiconductor integrated circuit device fabrication method and its fabrication apparatus, which can be applied to registration of circuit patterns and control of exposure, for example, in an exposure process, in the quality control of fabrication processes and the control technique of apparatus accuracy.
For example, to fabricate a semiconductor integrated circuit device by using a technique for fabricating a semiconductor integrated circuit device, it is necessary to accurately control the shapes and thicknesses of more than ten circuit pattern layers and superimpose the pattern layers by accurately adjusting the positions of the pattern layers. This is because a change of the shape and thickness of each pattern layer and misregistration of the pattern layers degrades the characteristics, reliability, and yield of a semiconductor integrated circuit device.
Therefore, when a fine circuit pattern is formed on a semiconductor wafer by an aligner in the semiconductor integrated circuit device fabrication process, the precision of the pattern shape and the relative positional accuracy with a circuit pattern already formed on the wafer are measured to ensure the accuracies before starting the exposure.
The pattern shape accuracy control is not necessarily only for an aligner for transferring a circuit pattern onto a wafer. Also in the case of an etching system for etching a base thin film using a photoresist on which a pattern is formed as a mask, it is necessary to ensure the accuracy before starting the process.
Also in the case of the process of forming a thin film on a wafer in a semiconductor fabrication process, it is necessary to ensure the accuracy by measuring the thickness and electric characteristics of the formed thin film before starting process.
In the case of the prior art for improving the yield, characteristics, and reliability of a semiconductor integrated circuit device by ensuring each element quality of the semiconductor fabrication process and then controlling the processor, measurement is performed for each element quality by using measuring instruments, variation of element qualities is controlled by setting target values and control limits, and correction for making each element quality approach the target value is carried out by adjusting the processor when variations from the target values occur.
For the element quality control in the semiconductor integrated circuit device fabrication process, data is collected by data communication from the measuring instruments to an external computer in accordance with the necessity of automation. This is prescribed by the SEMI standard and spread.
For example, a system for collecting data for small dimensions measured by dimension measuring instruments and storing them in a host computer is disclosed in Japanese Patent Laid-Open No. 122913/1988. In this case, the collected dimension data is used for precise control of pattern dimensions by a statistical control method using the host computer.
It is necessary to sort the above dimension data according to measured objects and then subjecting them to time-series analysis and statistical control. The prior art of the time-series analysis and statistical control is disclosed in Japanese Patent Laid-Open No. 123051/1991. In the case of the prior art, the dimensions data is classified according to the type of products using a host computer through the communication means to control the differences between target values and measured values which will be described later. In this case, the dimension value which is a single element quality is controlled for each measured object.
The prior art of the automatic collection of element quality data and feedback of the data to a processor and the application of the data to analysis of the characteristics and failures of semiconductor integrated circuit devices is described in, for example, NIKKEI Microdevice, pp. 87-95, June, 1991. In this prior art corrected amounts computed from deviations from target values are given to measured dimensions and alignment deviations respectively and the correlation between various element quality data values and electric characteristics of a semiconductor integrated circuit device through a regression analysis for the failure analysis.
Moreover, another prior art of a method for correcting a processing parameters of a processor for a target value of individual element quality parameter is disclosed in Japanese Patent Laid-Open No. 224319/1990, in which the correlation between the element quality parameter and the processing parameter of a processor is determined to compute a corrected value of the processing parameter.
A prior art using fuzzy inference to compute a corrected value is disclosed in Japanese Patent Laid-Open No. 277802/1992. In this prior art a new corrected value of a processor is found by the equation Pi'=Pi+Ci where the corrected value of the processor is Pi, and the corrected value determined from the deviation of the element quality parameter from the target value through fuzzy inference is Ci. In this case, it is estimated that a membership function used for fuzzy inference is determined in accordance with the controllability of the corrected value Pi for the element quality parameter.
Still another prior art for regression-analyzing the correlation between the element quality data and electrical characteristics of a semiconductor integrated circuit device is disclosed in Japanese Patent Laid-Open No. 277802/1992. In this prior art, the accuracy of coordinating data when performing correlation analysis by considering the distribution in a wafer based on not only the statistical data of each wafer and each lot but information about mapping.
In this prior art, the data is are automatically retrieved from the storage media or through communication means by the host computer, which have been manually inputted conventionally. In this case, the collected data is used to support the analysis by an engineer through contour lines or a scatter diagram.